Mark

Name: Mark

Job Title: Graduate Engineer

What appeals to you about Electronics?

I enjoy the combination of applied theory, creativity, and modern technology in developing novel solutions to challenging engineering problems. With ongoing developments in AI, photonics and material science, technological advancement is rapidly accelerating, making it an exciting time to work as an electronics engineer.

Why did you apply for a scholarship with Specialised Imaging?

I was keen to work with Specialised Imaging, as they are globally recognised for their market leading ultra-high-speed imaging systems, which are used in a variety of industries, ranging from industrial and defence applications, to scientific research. Having completed a placement with a defence company specialising in the design of electro-optical devices, and a research placement studying the effects of laser welding through metallography and SEM analysis, a placement working with SI-Sensors was a familiar progression from my previous exposure to imaging systems (no pun intended). The opportunity to work on the development of world-leading image sensors is rare and I was glad to secure a scholarship with SI-Sensors.

What type of work were you involved in during your placement with Specialised Imaging?

During my summer placement, I worked as an Analogue IC Design Engineer, with a focus on the pixel architecture as part of a feasibility study for a future image sensor. My day-to-day tasks involved schematic design, spectre simulations and pixel layout using Cadence design tools. I was able to apply circuits I’d learnt about, such as source-followers and current mirrors, and put them into practise in the design of a pixel. I was also introduced to more advanced concepts such as measuring noise sources within the circuit using ADE Explorer, and implementing design techniques such as correlated-double sampling (CDS) to minimise readout noise. After the pixel layout was complete, I carried out DRC and LVS checks, to ensure that the layout was compliant with the PDK design rules, and matched the schematic design


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