Get prepared for a career in the Semiconductor Industry
Online, 2 February – 2 March 2026, free to attend

The UKESF will be running this course for a second time in February/March 2026, following a successful and fully-booked course in September 2025. It will support you to build on the robust theoretical knowledge you’ve gained at university to develop the practical skills and expertise needed by the semiconductor sector.

This course, trusted by leading employers in the sector, will prepare you to hit the ground running as a graduate design engineer or early career engineer in digital design.

“My skills have improved, but more importantly my broad understanding of the industry and different processes have significantly improved.”

Course Participant, September 2025

Learning outcomes

  • Combinational and Sequential Logic Design for PLDs and ASICs, with an emphasis on synchronous design techniques
  • How to design and implement fundamental structures, e.g., decoders, multiplexers, shift registers, counters
  • How to design and implement synchronous Finite State Machines
  • An overview of ASIC and field programmable logic design including a survey of state-of-the-art-devices
  • Designing with programmable devices
  • Effective Design methodologies and flows
  • Understand the role of on-chip buses with a focus on the de facto standard AMBA 3 APB/AXI bus protocols

Am I Eligible?

You must be a 3rd, 4th, final-year or placement year Electronics undergraduate or postgraduate from a UK university AND a home student or British National or have settled status.

If you meet the eligibility criteria, you can register your interest in attending here.

Course Format

Live Session #1, Introduction to the Course
Monday 2 February, 10:00-12:00

16 hours of self-paced learning on the Doulos platform
Monday 2 February – Monday 2 March

Live Session #2, Course conclusion and Q&A
Monday 2 March, 10:00-12:00

Why Join the Course?

Completed by almost 1,000 engineers throughout the UK, this is a trusted training course chosen by leading semiconductor employers.

The programme has a strong emphasis on practical design and hands-on workshops; specifically developed to teach design techniques in an intensive and effective format.

It is valuable first stage pre-employment training for graduate design engineers, or graduate engineers moving into – or considering moving into – digital design from other disciplines (including software or analogue design).

It is a natural precursor to the specific language skills required by future employers, such as VHDL, Verilog, and SystemVerilog, used within FPGA or ASIC design projects.

Benefits of Participating

  • Free training from industry-respected commercial trainer, Doulos (Fully funded by HM Government as part of the UKESF’s Semiconductor: Skills, Talent and Education Programme)
  • Industry standard training
  • Contribute to your ongoing development
  • Access to EDA Playground once the course is complete, if you provide an academic email address on sign-up (Watch an EDA Playground Walkthrough on YouTube)
  • Support and encouragement to pursue a career in the semiconductor industry

“The exposure to real-world design and verification processes has deepened my understanding of the industry's demands”

Course Participant, September 2025

Register your interest in attending here

Please note that places are limited. The deadline to register your of interest is Sunday 11 January.

Facilitator

Matthew Taylor has been a member of the Doulos team since 2014, where he teaches classes in VHDL, Verilog, SystemVerilog and UVM. Prior to joining Doulos he was at Sony for 16 years where he was involved in the project management, design and verification of ICs for digital TV and mobile phones. Prior to Sony he was at Siemens for 8 years where he designed FPGAs and ICs for radio applications. He graduated from the University of Bath in 1989 with a first-class degree in Electronics and Electrical Engineering and also has an Meng in Engineering.

Participant Expectations

By registering for the course, you must commit to:

  • Attending the live sessions on 2 February and 2 March
  • Completing 16 hours self-paced training between the two sessions
  • Completing pre- and post- training feedback