OLIX are building a next-generation chip architecture that fuses digital, optical, and mixed-signal design in ways that haven't been done before.
Our Scholarships
Placement Location
Bristol
Type of Placements Offered
• Summer placements • MEng placements
Restrictions/Notes
(1) Open only to British citizens (no dual nationals); (2) Students should be in the penultimate year of their degree
Who we are and what we do
Introduction into OLIX:
AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.
Headquartered in London and growing teams across the UK, US and Canada, OLIX gives engineering graduates the chance to work on one of the most ambitious infrastructure problems in AI today, spanning photonics, chip design, compilers and systems engineering.
Compute Manifesto: The Inference Era
The Token Factory is Missing its Production Line
What you could be doing
Join OLIX’s ASIC team for a 6-month Placement (January–July) or Summer Internship (June-August) and get hands-on with real silicon engineering. We’re building the OLIX Decode Accelerator 1 (DX-1), a next-generation chip architecture that fuses digital, optical, and mixed-signal design in ways that haven’t been done before.
As a summer intern or placement student, you’ll take ownership of a defined technical project and genuinely contribute to what the team is building. Depending on where the team’s needs land, this could touch areas like:
- SystemVerilog/UVM verification environments and testbench development
- Digital RTL design for high-speed streaming datapaths
- FPGA prototyping and hardware bring-up
- Algorithm modelling and validation (Python/MATLAB)
- Coverage, assertions, and verification methodology
You’ll be part of a small, senior team with backgrounds spanning some of the biggest names in semiconductors, in an early-stage environment where the problems are genuinely unsolved. It’s a great way to see what modern ASIC/FPGA engineering actually looks like, build real technical depth, and work on something that matters to a team pushing the boundaries of AI hardware.