Get prepared for a career in the Semiconductor Industry
Online, 1 September – 22 September 2025, free to attend

Build on the robust theoretical knowledge you’ve gained at university to develop the practical skills and expertise needed by the semiconductor sector.

This course, trusted by leading employers in the sector, will prepare you to hit the ground running as a graduate design engineer or early career engineer in digital design. If you are a lecturer, it will orient you to industry-standard EDA tools, and support your teaching in chip design.

Learning outcomes

  • Combinational and Sequential Logic Design for PLDs and ASICs, with an emphasis on synchronous design techniques
  • How to design and implement fundamental structures, e.g., decoders, multiplexers, shift registers, counters
  • How to design and implement synchronous Finite State Machines
  • An overview of ASIC and field programmable logic design including a survey of state-of-the-art-devices
  • Designing with programmable devices
  • Effective Design methodologies and flows
  • Understand the role of on-chip buses with a focus on the de facto standard AMBA 3 APB/AXI bus protocols

Am I Eligible?

You must be:

  • a lecturer in, or interested in expanding into, chip design at a UK university
  • a 3rd, 4th (or 5th in Scotland) or placement year MEng undergraduate or postgraduate from a UK university

Course Format

Live Session #1, Introduction to the Course
Monday 1 September, 10:00-12:00

16 hours of self-paced learning on the Doulos platform
Monday 1 September – Monday 22 September

Live Session #2, Course conclusion and Q&A
Monday 22 September, 10:00-12:00

Why Join the Course?

Completed by almost 1,000 engineers throughout the UK, this is a trusted training course chosen by leading semiconductor employers.

The programme has a strong emphasis on practical design and hands-on workshops; specifically developed to teach design techniques in an intensive and effective format.

It is valuable first stage pre-employment training for graduate design engineers, or graduate engineers moving into – or considering moving into – digital design from other disciplines (including software or analogue design).

It is a natural precursor to the specific language skills required by future employers, such as VHDL, Verilog, and SystemVerilog, used within FPGA or ASIC design projects.

Benefits of Participating

  • Free training from industry-respected commercial trainer, Doulos (Fully funded by HM Government as part of the UKESF’s Semiconductor: Skills, Talent and Education Programme)
  • Industry standard training
  • Contribute to your ongoing development
  • Access to EDA Playground once the course is complete, if you provide an academic email address on sign-up (Watch an EDA Playground Walkthrough on YouTube)
  • Support and encouragement to pursue a career in the semiconductor industry

Register Your Interest

Register Your Interest Here

Facilitator

Matthew Taylor has been a member of the Doulos team since 2014, where he teaches classes in VHDL, Verilog, SystemVerilog and UVM. Prior to joining Doulos he was at Sony for 16 years where he was involved in the project management, design and verification of ICs for digital TV and mobile phones. Prior to Sony he was at Siemens for 8 years where he designed FPGAs and ICs for radio applications. He graduated from the University of Bath in 1989 with a first-class degree in Electronics and Electrical Engineering and also has an Meng in Engineering.

Participant Expectations

By registering for the course, you must commit to:

  • Attending the live sessions on 1 September and 22 September
  • Completing 16 hours self-paced training between the two sessions
  • Completing pre- and post- training feedback